Scan testing integrated circuits (ICs, also referred to herein as chips and circuits), comprises applying fault test vectors to a path in the circuit (circuit path) to identify manufacturing defects (also called faults) in the circuit path. A fault test vector is a pattern of logical ‘1’ and ‘0’ values. Applying the fault test vectors to the circuit path comprises: loading the vectors in flip flops in communication with combinational logical (e.g. logical gates) in the path to be tested; allowing the combinational logic being targeted for testing by the specific fault test vectors to perform operations on the vector values to produce fault test vector responses (also referred to as sensitizing the logic); propagating the responses through downstream combinational logic, capturing the responses in flip flops; shifting the responses out of the flip flops; then analyzing the responses to identify the defects and their locations. The flip flops are only included in the circuit for the purpose of scan testing.
Stuck-at-faults and transition delay faults are two types of faults which can be tested by the Stuck-at-Fault (SAF) and Transition Delay Fault (TF) scan testing models, respectively. These models are widely used for identifying defects in an IC. The SAF model detects hard defects, such as signals shorted to VDD/GND. The TF model detects delayed signals indicating resistive circuit paths. In the SAF model, the logic in the path (which can include circuit nodes and gates connected through wires) are assumed to be stuck at either logical ‘1’ or ‘0’ values. Fault test vectors are generated to test the assumptions, and the vectors are applied on the manufactured IC to detect and isolate the defective logic. In the TF model, fault test vectors are generated to test for propagation delays in the logic along the capture path. Propagation delays may be caused by, for example, resistive opens, shorts or process variations, etc. which play a vital role in proper functioning of the chip at the functional rated frequencies.
Commercial electronic design automation (EDA) tools typically generate the fault test vectors. Many fault test vectors may need to be generated to achieve a particular test coverage. Coverage refers to the portion of elements in the circuit path under test which are actually tested for faults. It may not be feasible or even possible to achieve full test coverage of a path because it is too difficult or not possible to generate all of the fault test vectors to do so, especially where the circuit path under test comprises a memory. This is because propagating a fault test vector or fault test response through a memory requires writing to and reading from the memory. But high SAF and TF coverage is desirable to ensure that quality chips are shipped to end customers.
A bypass path comprising a collar flop connected in parallel with the memory has been used to exclude the memory from the test path. But using the collar flop to exclude the memory from the test path prevents testing for timing delay faults caused by the memory. The bypass path and collar flop also inadvertently exclude memory boundary logic from testing. This is undesirable since it ultimately decreases the fault test coverage of the path under test.
In short, it is difficult to achieve good fault test coverage for a circuit comprising a memory because bypassing the memory in scan tests using a collar flop also bypasses certain of the memory boundary logic, and also fails to account for timing delays caused by the memory, but including the memory in scan tests makes it difficult to generate fault test vectors that can sensitize all of the logic in the path under test.